Power metal-oxide-semiconductors (MOS) devices, including lateral diffused MOS (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. Radio frequency (RF) LDMOS devices are generally fabricated on a semiconductor wafer comprising a substrate that is typically formed of single crystal silicon which has been heavily doped with an impurity, such as, for example, boron, so as to form a low-resistivity substrate (e.g., about 1018 to about 1019 atoms per cubic centimeter). A lightly-doped epitaxial layer (e.g., about 1014 to about 1015 atoms per cubic centimeter), typically about ten microns thick, is generally formed on the substrate.
One problem in fabricating an LDMOS device is forming a substrate contact for providing a low-resistance electrical path from an active region in the device formed near an upper surface of the wafer, through the lightly-doped epitaxial layer to the more heavily-doped substrate below. Previous attempts to solve this problem have involved forming a diffused sinker by doping the surface of the silicon with a heavy boron predeposition or implanting a relatively high-dose ion implant, either of which is then thermally driven at a high temperature (e.g., in excess of 1000 degrees Celsius) for a relatively long duration (e.g., typically in excess of about 10 hours) through the epitaxial layer until it merges with the heavily doped substrate below. In driving the diffusion or implant down into the silicon, however, the dopant will out-diffuse on either side by a certain amount, typically about 8 microns. Thus, the formation of the diffused sinker consumes a substantially large area in the wafer comparable to the needed depth of the sinker. This condition significantly reduces packing density in the wafer. The requirement of a high-dose implant step can also result in excessive implant time for the wafer.
The long period of time required for the high temperature drive-in process can undesirably result in a large up-diffusion of dopant from the heavily-doped substrate into the lightly-doped epitaxial layer which effectively thins the epitaxial layer, thereby lowering junction breakdown voltage and increasing junction leakage. Additionally, an increase in the number of misfit dislocations can occur, generally originating from mismatches between the lattices of the epitaxial layer and substrate. This often leads to a drop in yield and/or reliability, among other disadvantages.
Other known attempts at forming a substrate contact for providing a low-resistance path between the upper surface of the wafer and the substrate have involved forming one or more conductive plugs through the epitaxial layer down to the substrate. This methodology involves first forming v-grooves (e.g., by a wet etching process), or other trenches (e.g., by a dry etching process), entirely through the epitaxial layer to expose the substrate, and depositing a conductive material, such as, for example, tungsten, metal or silicide, in the v-grooves, thereby establishing an electrical connection with the substrate.
FIGS. 1A and 1B are cross-sectional views of at least a portion of a semiconductor wafer 100 illustrating processing steps which may be used in forming conventional substrate contacts. With reference to FIG. 1A, the wafer 100 may include a substrate 102, which is typically formed of silicon that is heavily doped with an impurity (e.g., boron, phosphorous, etc.) of a desired concentration. The wafer 100 may include an epitaxial layer 104 formed on at least a portion of the substrate 102. An insulating layer 106 (e.g., silicon dioxide) may be formed on at least a portion of the epitaxial layer 104. Deep trenches 108 may be formed through the insulating layer 106 and epitaxial layer 104, to at least partially expose the substrate 102. As shown in FIG. 1B, the trenches 108 are then filled with an electrically conductive material 110 (e.g., aluminum) to form conductive plugs entirely through the epitaxial layer 104. Each of the conductive plugs provide a substantially low-resistance (e.g., about 8 to 10 ohms) path between the upper surface of the wafer 100 and the substrate 102.
A primary disadvantage of the above approach, however, is the inability to control a surface doping in the substrate and in a source region of the LDMOS device so as to produce acceptable contact resistance between the substrate/source region and deposited conductive layer. Another disadvantage with this approach is the need to precisely control the fill of the v-grooves so as to ensure a substantially planar surface, which is essential for further processing, and a substantially void-free fill, typically a requirement in forming a sufficiently low-resistance contact. Furthermore, the depth of the v-grooves requires a certain minimum width because a substantially constant aspect ratio of depth-to-width (e.g., about 5-to-1) generally should be maintained during processing of the wafer.
There exists a need, therefore, for an enhanced substrate contact capable of improved performance and reliability that does not suffer from one or more of the above-noted deficiencies typically affecting conventional substrate contacts. Furthermore, it would be desirable if such a substrate contact was fully compatible with a conventional semiconductor process technology.